Improved Cost Reversible Multiplier Design

Reversible logic is an emerging research area and is a promising technology for the next generation of computers. The focus of this paper is improving the design of a multiplier that can be part of any future reversible computer. In this paper, we propose an improvement to the manner in which partial products are generated that improves the efficiency of implementation using repetition codes. The final implementation reduces the total number of gates, constant inputs, garbage outputs, and quantum cost over other proposed models.